1. Field of the Invention
The present invention relates generally to plasma etch methods for etching trenches within silicon oxide dielectric layers. More particularly, the present invention relates to plasma etch methods for etching, with uniform and optimal etch properties, trenches within silicon oxide dielectric layers.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to fabricate microelectronic fabrications while employing self-aligned methods. Self-aligned methods are desirable in the art of microelectronic fabrication for fabricating microelectronic fabrications insofar as self-aligned methods provide microelectronic fabrications which may be fabricated with a minimal number of photolithographic process steps, which in turn provides for a minimal number of photolithographic registration tolerances and possible misalignments within a series of microelectronic structures which are formed when fabricating a microelectronic fabrication while employing a self-aligned method.
Of the self-aligned microelectronic structures which may be fabricated while employing self-aligned methods, self-aligned contact microelectronic structures, including but not limited to dual damascene trench self aligned contact microelectronic structures, are particularly common in the art of microelectronic fabrication. To facilitate their fabrication, self-aligned contact microelectronic structures typically employ at least one silicon nitride etch stop layer masking at least one microelectronic structure within a microelectronic fabrication, in conjunction with a silicon oxide dielectric layer passivating the at least one microelectronic structure and the at least one silicon nitride etch stop layer, wherein the silicon oxide dielectric layer is typically etched while employing a plasma etch method to form the selfaligned contact microelectronic structure while employing the silicon nitride etch stop layer as a plasma etch stop layer.
While the use and fabrication of self-aligned microelectronic structures, such as but not limited to self aligned contact microelectronic structures, within microelectronic fabrication is desirable in the art of microelectronic fabrication, the use and fabrication of self-aligned microelectronic structures, such as but not limited to self-aligned contact microelectronic structures, is not entirely without problems in the art of microelectronic fabrication. In that regard, it is often difficult to form self-aligned microelectronic structures, such as but not limited to self aligned contact microelectronic structures, with uniform and optimal etch properties within the art of microelectronic fabrication while employing plasma etch methods.
It is thus desirable within the art of microelectronic fabrication to provide plasma etch methods for forming, with uniform and optimal etch properties, self-aligned microelectronic structures within microelectronic fabrications, and more particularly self-aligned contact microelectronic structures within microelectronic fabrications, and yet more particularly dual damascene trench self aligned contact microelectronic structures within microelectronic fabrications.
It is towards the foregoing objects that the present invention is directed.
Various plasma etch methods have been disclosed in the art of microelectronic fabrication for forming self-aligned structures with desirable properties within the art of microelectronic fabrication.
For example, Spuler et al., in U.S. Pat. No. 5,935,873, discloses a plasma etch method for forming, while avoiding the use of a carbon monoxide etchant gas, a field effect transistor (FET) source/drain region self aligned contact microelectronic structure within a semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the plasma etch method employs incorporating into a silicon nitride etch stop layer which encapsulates a pair of field effect transistor (FET) gate electrode structures within the semiconductor integrated circuit microelectronic fabrication, the silicon nitride etch stop layer in turn having formed thereupon a blanket silicon oxide dielectric layer passivating the silicon nitride etch stop layer and the pair of field effect transistor (FET) gate electrode structures, which silicon oxide dielectric layer is etched to form the field effect transistor (FET) self-aligned contact microelectronic structure within the semiconductor integrated circuit microelectronic fabrication, a quantity of carbon such that there may be avoided within an etchant gas composition employed within the plasma etch method the use of the carbon monoxide etchant gas in conjunction with an octafluorocyclobutane etchant gas, where the use of the carbon monoxide etchant gas would otherwise provide for enhanced selectivity for etching of the silicon oxide dielectric layer with respect to the silicon nitride etch stop layer.
In addition, Li et al., in U.S. Pat. No. 6,009,830, discloses a plasma etch method and a plasma etch apparatus wherein there may similarly also be reduced the use of a carbon monoxide etchant gas in conjunction with an octafluorocyclobutane etchant gas when forming, with enhanced uniformity, a field effect transistor (FET) source/drain region self aligned contact microelectronic structure through a silicon oxide dielectric layer which passivates a pair of field effect transistor (FET) gate electrode structures which are first encapsulated with a pair of silicon nitride etch stop layers within a semiconductor integrated circuit microelectronic fabrication, while employing the plasma etch method and the plasma etch apparatus. To realize the foregoing object, the plasma etch method and the plasma etch apparatus employ an introduction into a plasma reactor chamber of an inert carrier gas above the microelectronic fabrication when etching the microelectronic fabrication to form the field effect transistor (FET) source/drain region self aligned contact microelectronic structure and a simultaneous introduction into the reactor chamber of an active etchant gas composition from below the microelectronic fabrication when etching the microelectronic fabrication to form the field effect transistor source/drain region self-aligned contact microelectronic structure.
Desirable in the art of microelectronic fabrication are additional plasma etch methods and materials which may be employed for forming, with uniform and optimal etch properties, self-aligned microelectronic structures, such as but not limited to self-aligned contact microelectronic structures, further such as but not limited to dual-damascene trench self-aligned contact microelectronic structures, within microelectronic fabrications.
It is towards the foregoing objects that the present invention is directed.